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Stability of charge-pump phase-locked loops : The hold-in and pull-in ranges. / Kuznetsov, N. V.; Matveev, A. S.; Yuldashev, M. V.; Yuldashev, R. V.; Bianchi, G.

In: IFAC-PapersOnLine, Vol. 53, 2020, p. 2022-2026.

Research output: Contribution to journal › Conference article › peer-review

Harvard

Kuznetsov, NV, Matveev, AS, Yuldashev, MV, Yuldashev, RV & Bianchi, G 2020, 'Stability of charge-pump phase-locked loops: The hold-in and pull-in ranges', IFAC-PapersOnLine, vol. 53, pp. 2022-2026. https://doi.org/10.1016/j.ifacol.2020.12.2511

APA

Kuznetsov, N. V., Matveev, A. S., Yuldashev, M. V., Yuldashev, R. V., & Bianchi, G. (2020). Stability of charge-pump phase-locked loops: The hold-in and pull-in ranges. IFAC-PapersOnLine, 53, 2022-2026. https://doi.org/10.1016/j.ifacol.2020.12.2511

Vancouver

Kuznetsov NV, Matveev AS, Yuldashev MV, Yuldashev RV, Bianchi G. Stability of charge-pump phase-locked loops: The hold-in and pull-in ranges. IFAC-PapersOnLine. 2020;53:2022-2026. https://doi.org/10.1016/j.ifacol.2020.12.2511

Author

Kuznetsov, N. V. ; Matveev, A. S. ; Yuldashev, M. V. ; Yuldashev, R. V. ; Bianchi, G. / Stability of charge-pump phase-locked loops : The hold-in and pull-in ranges. In: IFAC-PapersOnLine. 2020 ; Vol. 53. pp. 2022-2026.

BibTeX

@article{e3955c6fce404bb48fff091e9f07fcb1,
title = "Stability of charge-pump phase-locked loops: The hold-in and pull-in ranges",
abstract = "The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis.",
keywords = "Charge-pump, Control of phase synchronization, CP-PLL, Hold-in range, Nonlinear analysis, PFD, Phase-frequency detector, Phase-locked loops, Pull-in range",
author = "Kuznetsov, {N. V.} and Matveev, {A. S.} and Yuldashev, {M. V.} and Yuldashev, {R. V.} and G. Bianchi",
note = "Publisher Copyright: Copyright {\textcopyright} 2020 The Authors. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.; 21st IFAC World Congress 2020 ; Conference date: 12-07-2020 Through 17-07-2020",
year = "2020",
doi = "10.1016/j.ifacol.2020.12.2511",
language = "English",
volume = "53",
pages = "2022--2026",
journal = "IFAC-PapersOnLine",
issn = "2405-8971",
publisher = "Elsevier",

}

RIS

TY - JOUR

T1 - Stability of charge-pump phase-locked loops

T2 - 21st IFAC World Congress 2020

AU - Kuznetsov, N. V.

AU - Matveev, A. S.

AU - Yuldashev, M. V.

AU - Yuldashev, R. V.

AU - Bianchi, G.

N1 - Publisher Copyright: Copyright © 2020 The Authors. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.

PY - 2020

Y1 - 2020

N2 - The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis.

AB - The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis.

KW - Charge-pump

KW - Control of phase synchronization

KW - CP-PLL

KW - Hold-in range

KW - Nonlinear analysis

KW - PFD

KW - Phase-frequency detector

KW - Phase-locked loops

KW - Pull-in range

UR - http://www.scopus.com/inward/record.url?scp=85095090562&partnerID=8YFLogxK

U2 - 10.1016/j.ifacol.2020.12.2511

DO - 10.1016/j.ifacol.2020.12.2511

M3 - Conference article

AN - SCOPUS:85095090562

VL - 53

SP - 2022

EP - 2026

JO - IFAC-PapersOnLine

JF - IFAC-PapersOnLine

SN - 2405-8971

Y2 - 12 July 2020 through 17 July 2020

ER -

ID: 78768918