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Limitations of the classical phase-locked loop analysis. / Kuznetsov, N. V.; Kuznetsova, O. A.; Leonov, G. A.; Neittaanmuaki, P.; Yuldashev, M. V.; Yuldashev, R. V.

2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. стр. 533-536 7168688 (Proceedings - IEEE International Symposium on Circuits and Systems; Том 2015-July).

Результаты исследований: Публикации в книгах, отчётах, сборниках, трудах конференций › статья в сборнике материалов конференции › Рецензирование

Harvard

Kuznetsov, NV, Kuznetsova, OA, Leonov, GA, Neittaanmuaki, P, Yuldashev, MV & Yuldashev, RV 2015, Limitations of the classical phase-locked loop analysis. в 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7168688, Proceedings - IEEE International Symposium on Circuits and Systems, Том. 2015-July, Institute of Electrical and Electronics Engineers Inc., стр. 533-536, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Португалия, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7168688, https://doi.org/10.1109/ISCAS.2015.7168688

APA

Kuznetsov, N. V., Kuznetsova, O. A., Leonov, G. A., Neittaanmuaki, P., Yuldashev, M. V., & Yuldashev, R. V. (2015). Limitations of the classical phase-locked loop analysis. в 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (стр. 533-536). [7168688] (Proceedings - IEEE International Symposium on Circuits and Systems; Том 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168688, https://doi.org/10.1109/ISCAS.2015.7168688

Vancouver

Kuznetsov NV, Kuznetsova OA, Leonov GA, Neittaanmuaki P, Yuldashev MV, Yuldashev RV. Limitations of the classical phase-locked loop analysis. в 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. стр. 533-536. 7168688. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2015.7168688, https://doi.org/10.1109/ISCAS.2015.7168688

Author

Kuznetsov, N. V. ; Kuznetsova, O. A. ; Leonov, G. A. ; Neittaanmuaki, P. ; Yuldashev, M. V. ; Yuldashev, R. V. / Limitations of the classical phase-locked loop analysis. 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. стр. 533-536 (Proceedings - IEEE International Symposium on Circuits and Systems).

BibTeX

@inproceedings{51d77ad622e8425a9512e5bce5d6b815,
title = "Limitations of the classical phase-locked loop analysis",
abstract = "Nonlinear analysis of the classical phase-locked loop (PLL) is a challenging task. In classical engineering literature simplified mathematical models and simulation are widely used for its study. In this work the limitations of classical engineering phase-locked loop analysis are demonstrated, e.g., hidden oscillations, which can not be found by simulation, are discussed. It is shown that the use of simplified mathematical models and the application of simulation may lead to wrong conclusions concerning the operability of PLL-based circuits.",
author = "Kuznetsov, {N. V.} and Kuznetsova, {O. A.} and Leonov, {G. A.} and P. Neittaanmuaki and Yuldashev, {M. V.} and Yuldashev, {R. V.}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",
year = "2015",
month = jul,
day = "27",
doi = "10.1109/ISCAS.2015.7168688",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "533--536",
booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",
address = "United States",

}

RIS

TY - GEN

T1 - Limitations of the classical phase-locked loop analysis

AU - Kuznetsov, N. V.

AU - Kuznetsova, O. A.

AU - Leonov, G. A.

AU - Neittaanmuaki, P.

AU - Yuldashev, M. V.

AU - Yuldashev, R. V.

N1 - Publisher Copyright: © 2015 IEEE.

PY - 2015/7/27

Y1 - 2015/7/27

N2 - Nonlinear analysis of the classical phase-locked loop (PLL) is a challenging task. In classical engineering literature simplified mathematical models and simulation are widely used for its study. In this work the limitations of classical engineering phase-locked loop analysis are demonstrated, e.g., hidden oscillations, which can not be found by simulation, are discussed. It is shown that the use of simplified mathematical models and the application of simulation may lead to wrong conclusions concerning the operability of PLL-based circuits.

AB - Nonlinear analysis of the classical phase-locked loop (PLL) is a challenging task. In classical engineering literature simplified mathematical models and simulation are widely used for its study. In this work the limitations of classical engineering phase-locked loop analysis are demonstrated, e.g., hidden oscillations, which can not be found by simulation, are discussed. It is shown that the use of simplified mathematical models and the application of simulation may lead to wrong conclusions concerning the operability of PLL-based circuits.

UR - http://www.scopus.com/inward/record.url?scp=84946201114&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2015.7168688

DO - 10.1109/ISCAS.2015.7168688

M3 - Conference contribution

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 533

EP - 536

BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -

ID: 3982514