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Hardware description language based on message passing and implicit pipelining. / Boulytchev, Dmitri; Medvedev, Oleg.

Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10. 2010. стр. 438-441 5742095 (Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10).

Результаты исследований: Публикации в книгах, отчётах, сборниках, трудах конференций › статья в сборнике материалов конференции › научная › Рецензирование

Harvard

Boulytchev, D & Medvedev, O 2010, Hardware description language based on message passing and implicit pipelining. в Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10., 5742095, Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10, стр. 438-441, IEEE East-West Design and Test Symposium, EWDTS'10, St. Petersburg, Российская Федерация, 17/09/10. https://doi.org/10.1109/EWDTS.2010.5742095

APA

Boulytchev, D., & Medvedev, O. (2010). Hardware description language based on message passing and implicit pipelining. в Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10 (стр. 438-441). [5742095] (Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10). https://doi.org/10.1109/EWDTS.2010.5742095

Vancouver

Boulytchev D, Medvedev O. Hardware description language based on message passing and implicit pipelining. в Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10. 2010. стр. 438-441. 5742095. (Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10). https://doi.org/10.1109/EWDTS.2010.5742095

Author

Boulytchev, Dmitri ; Medvedev, Oleg. / Hardware description language based on message passing and implicit pipelining. Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10. 2010. стр. 438-441 (Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10).

BibTeX

@inproceedings{af507db89b414a35975d94c930a95d70,

title = "Hardware description language based on message passing and implicit pipelining",

abstract = "We present a hardware description language (currently called HaSCoL) which is based on both reliable and unreliable message passing and implicit pipelining of message handlers. The language consists of a small core and a number of extensions, which cover many features of high level software languages as well as high level hardware description languages (HDLs). These extensions have simple projections into the core language and allow compact and concise description of complex algorithms. The core language in turn can be converted into efficient VHDL. We discuss place-and-route results for some benchmarks implemented both in HaSCoL and VHDL and suggest an optimization which should improve the results significantly and make them close to those for hand-coded VHDL.",

author = "Dmitri Boulytchev and Oleg Medvedev",

year = "2010",

doi = "10.1109/EWDTS.2010.5742095",

language = "English",

isbn = "9781424495566",

series = "Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10",

pages = "438--441",

booktitle = "Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10",

}

RIS

TY - GEN

T1 - Hardware description language based on message passing and implicit pipelining

AU - Boulytchev, Dmitri

AU - Medvedev, Oleg

PY - 2010

Y1 - 2010

N2 - We present a hardware description language (currently called HaSCoL) which is based on both reliable and unreliable message passing and implicit pipelining of message handlers. The language consists of a small core and a number of extensions, which cover many features of high level software languages as well as high level hardware description languages (HDLs). These extensions have simple projections into the core language and allow compact and concise description of complex algorithms. The core language in turn can be converted into efficient VHDL. We discuss place-and-route results for some benchmarks implemented both in HaSCoL and VHDL and suggest an optimization which should improve the results significantly and make them close to those for hand-coded VHDL.

AB - We present a hardware description language (currently called HaSCoL) which is based on both reliable and unreliable message passing and implicit pipelining of message handlers. The language consists of a small core and a number of extensions, which cover many features of high level software languages as well as high level hardware description languages (HDLs). These extensions have simple projections into the core language and allow compact and concise description of complex algorithms. The core language in turn can be converted into efficient VHDL. We discuss place-and-route results for some benchmarks implemented both in HaSCoL and VHDL and suggest an optimization which should improve the results significantly and make them close to those for hand-coded VHDL.

UR - http://www.scopus.com/inward/record.url?scp=79955970939&partnerID=8YFLogxK

U2 - 10.1109/EWDTS.2010.5742095

DO - 10.1109/EWDTS.2010.5742095

M3 - Conference contribution

AN - SCOPUS:79955970939

SN - 9781424495566

T3 - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10

SP - 438

EP - 441

BT - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10

T2 - IEEE East-West Design and Test Symposium, EWDTS'10

Y2 - 17 September 2010 through 20 September 2010

ER -

ID: 76606967