Computation of lock-in range for classic PLL with lead-lag filter and impulse signals › SPbU Researchers Portal

Links

http://www.sciencedirect.com/science/article/pii/S2405896316312605

DOI

https://doi.org/10.1016/j.ifacol.2016.07.972
Final published version
https://doi.org/10.1016/j.ifacol.2016.07.972
Other version

For a classic PLL with square waveform signals and lead-lag filter for all possible parameters lock-in range is computed and corresponding diagrams are given.

Original language	English
Pages (from-to)	42-44
Number of pages	3
Journal	IFAC Proceedings Volumes (IFAC-PapersOnline)
Volume	49
Issue number	14
DOIs	https://doi.org/10.1016/j.ifacol.2016.07.972 https://doi.org/10.1016/j.ifacol.2016.07.972
State	Published - 2016

Scopus subject areas

Control and Systems Engineering

Research areas

analog PLL, cycle slipping, definition, hold-in range, lead-lag filter, lock-in range, nonlinear analysis, Phase-locked loop, pull-in range

ID: 7591960