Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Research › peer-review
Analysis and design of computer architecture circuits with controllable delay line. / Kuznetsov, N. V.; Leonov, G. A.; Seledzhi, S. M.; Neittaanmäki, P.
ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics, Proceedings. 2009. p. 221-224 (ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics, Proceedings; Vol. 3 SPSMC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Research › peer-review
}
TY - GEN
T1 - Analysis and design of computer architecture circuits with controllable delay line
AU - Kuznetsov, N. V.
AU - Leonov, G. A.
AU - Seledzhi, S. M.
AU - Neittaanmäki, P.
PY - 2009
Y1 - 2009
N2 - In this work classical and modern control theory methods are applied for rigorous mathematical analysis and design of different computer architecture circuits such as clock generators, synchronization systems and others. The present work is devoted to the questions of analysis and synthesis of feedback systems, in which there are controllable delay lines. In the work it is mathematically strictly shown that RC-chain can be used as a controllable delay line for different problems of circuit engineering if the chain is sequentially connected with hysteretic relay. This relay is either artificially introduced or shows itself as non-ideality of logic elements. The possibility of phase-locked loop application for time delay control is considered.
AB - In this work classical and modern control theory methods are applied for rigorous mathematical analysis and design of different computer architecture circuits such as clock generators, synchronization systems and others. The present work is devoted to the questions of analysis and synthesis of feedback systems, in which there are controllable delay lines. In the work it is mathematically strictly shown that RC-chain can be used as a controllable delay line for different problems of circuit engineering if the chain is sequentially connected with hysteretic relay. This relay is either artificially introduced or shows itself as non-ideality of logic elements. The possibility of phase-locked loop application for time delay control is considered.
KW - Clocked circuit
KW - Delay line
KW - Nonlinear analysis
KW - Phase locked loop
UR - http://www.scopus.com/inward/record.url?scp=74549150075&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:74549150075
SN - 9789898111999
T3 - ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics, Proceedings
SP - 221
EP - 224
BT - ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics, Proceedings
T2 - ICINCO 2009 - 6th International Conference on Informatics in Control, Automation and Robotics
Y2 - 2 July 2009 through 5 July 2009
ER -
ID: 90381267