Speedup of deep neural network learning on the MIC-architecture

E. Milova, S. Sveshnikova, I. Gankevich

Research output

1 Citation (Scopus)

Abstract

Deep neural networks are more accurate, but require more computational power in the learning process. Moreover, it is an iterative process. The goal of the research is to investigate efficiency of solving this problem on MIC architecture without changing baseline algorithm. Well-known code vectorization and parallelization methods are used to increase the effectiveness of the program on MIC architecture. In the course of the experiments we test two coprocessor data transfer models: explicit and implicit one. We show that implicit memory copying is more efficient than explicit one, because only modified memory blocks are copied. MIC architecture shows competitive performance compared to multi-core ×86 processor.
Original languageEnglish
Title of host publicationInternational Conference on High Performance Computing Simulation (HPCS'16)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages989-992
ISBN (Print)978-1-5090-2088-1
DOIs
Publication statusPublished - 2016

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